Universal Computing Corp.

One design to run all.

A general-purpose computer built from local interactions. The same machine model from a single unit to a cluster.

See how it works
UniversalAccessibleHigh-performance

Touch the rule

Write a λ-term and watch it become a net of interaction combinators. Red wires are active pairs. Click any of them to rewrite it: each rewrite only touches its own neighbourhood.

Type \ for λ
  • LAM (+; + −). The main port gives the function; aux0 is the binder, aux1 takes the body.
  • APP (−; − +). The main port takes the function; aux0 takes the argument, aux1 gives the result.
  • DUP− (−; + +) shares a value between two uses; DUP+ (+; − −) comes from copying a λ. The number is its label.
  • ERA− (−) and ERA+ (+) erase.
  • Polarity: every wire joins a + port, which gives a term, to a − port, which needs one. The arrow points the way the term goes.
  • Hatched: an agent lying back side up, mirrored. Front side up, with the main port on top, aux0 is on the left.
  • Active pair: a + main port meets a − main port. Click to rewrite.
Click a red wire
0 / 0

Step rewrites one pair. Round rewrites every active pair at once, the way separate units would in parallel. The demo engine is 2-PIC, interaction combinators with two polarities and labelled duplicators; it is not the S8S rule set.

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One RXU

Three properties of one design.

Universal

Removes
The accelerator archipelago: a different chip, language and toolchain for every kind of work.
How
One architecture and one language for logic, graphs and numerical work.
Evidence
Designed
Inspect the claim

Question card placeholder: “Does general mean equally fast on every workload?” Short verdict, mechanism, evidence level.

Accessible

Removes
Semantic fracture: intent lost between language, compiler, ISA and hardware.
How
Functional semantics are the machine's native form, so programs can be checked formally.
Evidence
Designed
Inspect the claim

Question card placeholder: “Do I have to learn a new language?” Short verdict, mechanism, evidence level.

High-performance

Removes
The movement and coordination tax: state shuttled across memory levels and devices.
How
State sits beside the logic that rewrites it; independent pairs rewrite in parallel as units are added.
Evidence
Simulated Projected
Inspect the claim

Question card placeholder: “Does scaling stay linear once traffic crosses chips?” Short verdict, mechanism, evidence level.

If one design unifies so much, why isn't the world already running on it?

Because it still has to be built. Scroll to follow the road.

Team

Cheng Peng

Co-founder

Fundraising, product narrative, partnerships, IP strategy and building the organization.

Jiahong Ye

Co-founder

System architecture, compiler work, FPGA implementation and technical execution.

Who we're looking for

  • Senior hardware engineer: RTL, FPGA, verification
  • Full-stack and developer tooling
  • Formal methods and PL researchers
  • Workload experts with irregular, graph-shaped problems

Help build the machine.

Tell us where you'd start.

Discuss investment Build the hardware Work on the language Bring a workload Say hello

contact@univcompute.com